Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel of a semiconductor substrate under the influence of a bias applied to a gate electrode that overlies the channel. The gate electrode is disposed on a gate dielectric and generally includes a high-k dielectric material, i.e., a material that has a dielectric constant that is greater than silicon (dielectric constant of 3.9). The gate dielectric is disposed between the gate electrode and the semiconductor substrate, and the gate electrode and the gate dielectric together form a gate electrode structure. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
As advanced MOS technology continues to scale and move into the deep-sub-micron geometry dimensions, proper protection of gate electrode structures becomes more complex. Protection of the gate electrode structures is generally achieved by forming sidewall spacers adjacent to sidewalls of the gate electrode structures prior to implantation techniques that are employed to form the source and drain regions in the semiconductor substrate. Protection of the gate electrode structures using the sidewall spacers is generally desired to mask the gate electrode structures from various front-end-of-line (FEOL) processing techniques that could degrade the gate electrode structures, particularly techniques that employ etchants. The spacers also enable self-aligned formation of the source and drain regions during ion implantation. If the gate electrode structure is not properly protected, the gate electrode structure may be compromised during further FEOL processing. Often poor adhesion between the sidewall spacers and the semiconductor substrate is observed, resulting in formation of a seam between the sidewall spacers and the gate electrode structure. High-k dielectric material in the gate dielectric may be susceptible to etching through the seam during various cleaning techniques that are employed during FEOL processing, resulting in so-called “missing high k” defects that degrade yield performance of the ICs.
Accordingly, it is desirable to provide methods of forming semiconductor devices with robust protection of the gate electrode structures, with the high-k dielectric layer of the gate electrode structures adequately protected from etching during FEOL processing. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.